The method of manufacturing a TFT array substrate is similar to that of manufacturing a very large-scale integrated circuit. The method is based on a plane drawing process, in which conversion of designed patterns is implemented according to a designed mask plate on a glass substrate, and a series of steps of adding and removing film materials are performed according to the patterns to be formed.
With the structure of the existing TFT array substrate, the resistance value of a common electrode layer made of the existing material is generally very high, so the loads of respective points in a plane are different, thus affecting the voltages of the respective points in the plane, leading to flicker or serious crosstalk in the plane and adversely affecting the picture quality of a panel. One solution in the prior art is to design a metal line in parallel with a gate line on the same layer when the gate line is made and electrically connect the metal line with the common electrode layer through a via hole, so as to reduce the resistance value of the common electrode layer. However, such design may greatly affect the edge distance of pixels and lead to the decline of an aperture ratio. Another solution is to directly make a metal layer on the common electrode layer in direct contact with the metal layer to reduce the resistance value of the common electrode layer. As this solution requires additional processes, the production cost is increased.
Moreover, due to rapid development of the liquid crystal technologies, the size of the TFT array substrate is made smaller and smaller. Thus how to improve the aperture ratio while reducing the resistance value of the common electrode layer effectively so as to achieve the objective of improving the display effect is an increasingly severe task.